1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, and particularly relates to a semiconductor memory device including a plurality of sense amplifiers that can be connected to any of a plurality of bit lines and a control method thereof.
2. Description of Related Art
Currently, there are various types of semiconductor memory devices, and DRAM (Dynamic Random Access Memory) can be mentioned as a representative thereof. Most of DRAMs are of a synchronous type in which data is inputted and outputted in synchronization with a clock signal, and can be randomly accessed with a cycle of about 7 ns.
However, DRAM is a volatile memory, and therefore there are problems as follows. Stored data is lost once the power supply is disconnected, and thus DRAM is not suitable for storing a program or archival data that should be saved for a long period of time. Further, even when the power supply is being inputted, a periodic refreshing operation needs to be performed to maintain the data, and thus there is a limit to lowering of power consumption and also complicated control by a controller is necessary.
A flash memory is well-known as a large-capacity non-volatile semiconductor memory. However, even in the flash memory, there are disadvantages such that a large current is necessary for writing or deleting data, and also it requires a very long time for writing and erasing data. Therefore, it is not appropriate to use flash memory as an alternative to DRAM as a main memory. In addition, non-volatile memories such as MRAM (Magnetoresistive Random Access Memory) and FRAM (Ferroelectric Random Access Memory) have been proposed; however, these memories have a difficulty in obtaining the memory capacity equivalent to that of DRAM.
Meanwhile, as a semiconductor memory to be an alternative to DRAM, PRAM (Phase Change Random Access Memory) that performs recording using a phase change material has been proposed (see Japanese Patent Application Laid-open Nos. 2006-24355, 2005-158199, 2006-31795, and 2006-294181). In the PRAM, data is stored by a phase state of the phase change material included in a recording layer. That is, in the phase change material, an electric resistance in a crystal phase and that in an amorphous phase differ vastly, and the data can be recorded by utilizing this characteristic.
To change the phase state, the phase change material is heated by a writing current that is applied to the phase change material. On the other hand, to read the data, a resistance value is measured after sending a reading current to the phase change material. The reading current is set to a value that is sufficiently smaller than the writing current so that no phase change occurs. Due to this, unlike DRAM, PRAM can perform a non-destructive reading operation. Further, the phase state of the phase change material does not change unless high heat is applied, and thus, even when the power supply is disconnected, the data is not lost.
DRAM is a semiconductor memory device of a voltage sensing type, and thus a potential difference occurring in a bit line pair is amplified by a sense amplifier to read the data. In contrast thereto, PRAM is a semiconductor memory device of a current sensing type, and thus, to read the data, it is necessary to convert a retained content to a potential difference by sending a reading current to a memory cell, and also to amplify this potential difference.
Therefore, in the sense amplifier of PRAM, the circuit scale is much larger than that of the sense amplifier of DRAM. Accordingly, it is not practical to arrange the sense amplifier for each bit line like DRAM, and this requires sharing the same sense amplifier for a plurality of bit lines.
However, when the same sense amplifier is shared for the plural bit lines, if consecutive read operations are requested, it requires starting a next sensing operation after the completion of the current sensing operation. As a result, a data reading cycle is restricted by an operation speed of the sense amplifier. Hence, it has a problem that the data reading cycle becomes much longer as compared to that of the DRAM, which in turn cannot keep the compatibility with the DRAM.
Such a problem similarly occurs not only in PRAM but also in semiconductor memory devices of other types (for example, RRAM: Resistive Random Access Memory), in which a sensing operation takes a long period of time.